Specifications for AMD's next-generation Zen 6-based server products have surfaced at Baidu, via HXL at X. Venice, the successor to AMD's current Turin server offerings, will reportedly pack as many as 256 cores based on the Zen 6c design, suggested with 1GB of total L3 cache, and that's without any additional 3D cache chiplets. We must tread with caution and not treat these details as definitive, since these products are likely a year or more away from launch.
AMD's current-generation Zen 5-based server EPYC 9005 CPUs, codenamed Turin, slot into the SP5 socket, similar to EPYC 9004 (Genoa), which used Zen 4 cores, adopting a design similar to Arm's big.LITTLE. AMD also launched these CPUs with denser Zen 4c/5c cores, with Turin Dense reaching up to 192 cores/384 threads. Similarly, AMD also offers the cost-effective SP6 socket, which currently supports AMD's EPYC 8004 (Siena) offerings with up to 64 Zen 4c cores, also rumored to be compatible with the speculated Zen 5-based EPYC 8005 (Sorano) family.
AMD is rumored to introduce new SP7 and SP8 sockets for its next-generation server offerings, succeeding SP5 and SP6, respectively. The larger SP7 platform is expected to accommodate EPYC 9006 (Venice) CPUs, which reportedly feature as many as 256 Zen 6c cores, divided across eight CCDs. This lands us at 32-core Zen 6c CCDs, which are also purported to feature 128MB of L3 cache, for 1GB of total L3 cache (128MB x 8) for a 256-core chip.
SP8: up to 128 Zen 6C cores with 128MB per CCD (96 cores for Zen 6 models), 350-400wSP7: upto 256 Zen 6C cores, ~600w https://t.co/CQodEenhBkMay 10, 2025
While the top core count for standard Zen 6-based Venice CPUs on SP7 remains unknown, the leak suggests a significant update in the CCD design. Each Zen 6 CCD allegedly carries 12 cores and 48MB of L3 cache, a notable increase from the eight cores and 32MB seen since Zen 2.
The lower-cost SP8 platform will allegedly support four 32-core Zen 6c CCDs for 128 cores and 512MB of total L3 cache. That's a solid increase over Siena and likely even Sorano. Standard Zen 6 options on SP8 are projected to offer 96 cores (eight 12-core chiplets) and 384MB of L3 cache. This significant improvement in core density is likely a direct consequence of adopting TSMC's 2nm (N2) process node. Although specifics have not been detailed, we can expect similar improvements in I/O capabilities, including more memory channels and increased PCIe lane counts.
The rationale behind pursuing more cores and larger caches is evident in light of upcoming Diamond Rapids and Clearwater Forest, which are Xeon processors, anticipated to be some of Intel's most sophisticated and advanced designs in recent history. Likewise, AMD is also expected to shift to advanced packaging options from TSMC with Zen 6, potentially employing silicon interposers (TSMC's CoWoS-S) or silicon bridges (TSMC's InFO_LSI or CoWoS-L) to link its CCDs and IODs. Following the typical two-year cadence between generations, we can expect the first Zen 6-based products to arrive by H2 2026.
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